/********************************************************************************
  * @file     SD93F115B_rcc.h  						    	
  * @author   TEST TEAM 												    	
  * @version  v0															    	
  * @date     Septemper 2022												    	
  * @brief   
  *           
  * Copyright (C) 2022  Hangzhou SDIC Microelectronics Co., Ltd
*********************************************************************************/


#ifndef __SD93F115B_RCC_H__
#define __SD93F115B_RCC_H__

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes */
#include "SD93F115B.h"

/*RCC_SYSTEMSOURCE ENABLE*/ 
#define RCC_ClockValue_IHRC                      24000000   //Hz
#define RCC_ClockValue_ILRC                      32000
#define RCC_ClockValue_XTOSC2                    24000000
#define RCC_ClockValue_XTOSC1                    32768

#define RCC_CLKSource_IHRC				 ((uint32_t)0x00000000)		
#define RCC_CLKSource_ILRC            	 ILRC_CR_ILRCEN
#define RCC_CLKSource_XTOSC1             XTOSC_CR_XTOSC1EN

#ifndef SD93F115B_JQS
#define RCC_CLKSource_XTOSC2             XTOSC_CR_XTOSC2EN

#define IS_RCC_CLKSource(RCC_CLKSource) (((RCC_CLKSource)==RCC_CLKSource_IHRC)||\
                                         ((RCC_CLKSource)==RCC_CLKSource_ILRC)||\
                                         ((RCC_CLKSource)==RCC_CLKSource_XTOSC1)||\
                                         ((RCC_CLKSource)==RCC_CLKSource_XTOSC2)) 
#endif	
#ifdef SD93F115B_JBS	
#define IS_RCC_CLKSource(RCC_CLKSource) (((RCC_CLKSource)==RCC_CLKSource_IHRC)||\
                                         ((RCC_CLKSource)==RCC_CLKSource_ILRC)||\
                                         ((RCC_CLKSource)==RCC_CLKSource_XTOSC1)) 	
#endif								   
/** @defgroup RCC_SYSTEMSOURCE SELECTION */
#define RCC_SYSCLK_IHRC						((uint32_t)0x00000000)		
#define RCC_SYSCLK_ILRC            			MCLK_CFGR_SRCSEL_0
#define RCC_SYSCLK_XTOSC1             		MCLK_CFGR_SRCSEL_1
#define RCC_SYSCLK_XTOSC2_DIV2            	((uint32_t)0x00000060)
#define RCC_SYSCLK_TESTOSC            	    MCLK_CFGR_SRCSEL_2  //  该位保留

#define IS_RCC_SYSCLK(RCC_SYSCLK) (((RCC_SYSCLK)==RCC_SYSCLK_IHRC )||\((RCC_SYSCLK)==RCC_SYSCLK_ILRC)||\
                                   ((RCC_SYSCLK)==RCC_SYSCLK_XTOSC1)||\((RCC_SYSCLK)==RCC_SYSCLK_XTOSC2_DIV2)||\
                                   ((RCC_SYSCLK)==RCC_SYSCLK_TESTOSC))

/**  @defgroup Configure the PeriPheral(APB1) clock prescaler */

#define RCC_SYSCLK_DIV1						((uint32_t)0x00000000)	
#define RCC_SYSCLK_DIV2           			MCLK_CFGR_SYSPRE_0
#define RCC_SYSCLK_DIV4             		MCLK_CFGR_SYSPRE_1
#define RCC_SYSCLK_DIV8          			MCLK_CFGR_SYSPRE
//#define RCC_SYSCLK_EN						MCLK_CFGR_SW

#define IS_RCC_SYSCLKDIV(SYSCLKDIV) (((SYSCLKDIV)==RCC_SYSCLK_DIV1)||\((SYSCLKDIV)==RCC_SYSCLK_DIV2)||\
                                     ((SYSCLKDIV)==RCC_SYSCLK_DIV4)||\((SYSCLKDIV)==RCC_SYSCLK_DIV8))
									 //((SYSCLKDIV)==RCC_SYSCLK_EN))  
											
/** @defgroup RCC_AHB_Peripherals 
  * @
  */
#define RCC_AHBPeriph_SRAM							AHB_ENR_SRAMEN	
#define RCC_AHBPeriph_FLITF           				AHB_ENR_FLITFEN
 
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))    
	
/** @defgroup RCC_APB_Peripherals clock enable 
  * @
  */
#define RCC_APBPeriph_INT_KEY				APB_ENR_INT_KEY_CKEN	
#define RCC_APBPeriph_TM0           		APB_ENR_TM0_CKEN
#define RCC_APBPeriph_TM1            		APB_ENR_TM1_CKEN
#define RCC_APBPeriph_TM2         			APB_ENR_TM2_CKEN
#define RCC_APBPeriph_RTC          			APB_ENR_RTC_CKEN            
#define RCC_APBPeriph_WWDG          		APB_ENR_WWDG_CKEN
#define RCC_APBPeriph_PWM0          		APB_ENR_PWM0_CKEN
#define RCC_APBPeriph_PWM1          		APB_ENR_PWM1_CKEN
#define RCC_APBPeriph_BUZ0          		APB_ENR_BUZ0_CKEN
#define RCC_APBPeriph_BUZ1          		APB_ENR_BUZ1_CKEN
#define RCC_APBPeriph_I2C          			APB_ENR_I2C_CKEN
#define RCC_APBPeriph_SPI          			APB_ENR_SPI_CKEN
#define RCC_APBPeriph_UART0          		APB_ENR_UART0_CKEN
#define RCC_APBPeriph_UART1          		APB_ENR_UART1_CKEN

#define RCC_APBPeriph_GPIO          		APB_ENR_GPIO_CKEN
#define RCC_APBPeriph_LCD          			APB_ENR_LCD_CKEN
#define RCC_APBPeriph_SDADC          		APB_ENR_SDADC_CKEN
#define RCC_APBPeriph_SARADC          		APB_ENR_SARADC_CKEN
//#define RCC_APBPeriph_PWR         		    APB_ENR_PWR_CKEN   //BG SIN时钟的使能

#define IS_RCC_APB_PERIPH(PERIPH) ((((PERIPH) & 0xFFF00020) == 0x00) && ((PERIPH) != 0x00))   
#define IS_RCC_APB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFFF00020) == 0x00) && ((PERIPH) != 0x00)) 

/**************** Configure the  PeriPheral of APB1 clock source *************************/							  
#define RCC_TMCLK_IHRC						((uint8_t)0x00) 	
#define RCC_TMCLK_ILRC           			((uint8_t)0x10)
#define RCC_TMCLK_XTOSC1            		((uint8_t)0x20)
#define RCC_TMCLK_XTOSC2         			((uint8_t)0x30)
#define RCC_TMCLK_P23         				((uint8_t)0x40)

#define IS_RCC_APB1_PERCLK(PERCLK)  (((PERCLK)==RCC_TMCLK_IHRC)||((PERCLK)==RCC_TMCLK_ILRC)||\
                                     ((PERCLK)==RCC_TMCLK_XTOSC1)||((PERCLK)==RCC_TMCLK_XTOSC2)||\
									 ((PERCLK)==RCC_TMCLK_P23))
	

/********Configure the PeriPheral(APB1) clock prescaler************************/
#define RCC_TMCLK_DIV1						((uint8_t)0x00) 	
#define RCC_TMCLK_DIV2           			((uint8_t)0x01)
#define RCC_TMCLK_DIV4            		    ((uint8_t)0x02)
#define RCC_TMCLK_DIV8         			    ((uint8_t)0x03)
#define RCC_TMCLK_DIV16					    ((uint8_t)0x04)	
#define RCC_TMCLK_DIV32           			((uint8_t)0x05)
#define RCC_TMCLK_DIV64            		    ((uint8_t)0x06)
#define RCC_TMCLK_DIV128         			((uint8_t)0x07)

#define IS_RCC_APB1_PERDIV(PERDIV) 	(((PERDIV)==RCC_TMCLK_DIV1)||((PERDIV)==RCC_TMCLK_DIV2)||\
                                     ((PERDIV)==RCC_TMCLK_DIV4)||((PERDIV)==RCC_TMCLK_DIV8)||\
									 ((PERDIV)==RCC_TMCLK_DIV16)||((PERDIV)==RCC_TMCLK_DIV32)||\
									 ((PERDIV)==RCC_TMCLK_DIV64)||((PERDIV)==RCC_TMCLK_DIV128))


									
/**************** Configure the  PeriPheral of APB2 clock source *************************/	  
#define RCC_PWMCLK_IHRC					   ((uint32_t)0x00000000)	
#define RCC_PWMCLK_ILRC           			APB_CFGR2_PWM0CKS_0
#define RCC_PWMCLK_XTOSC1            		APB_CFGR2_PWM0CKS_1
#define RCC_PWMCLK_XTOSC2         			APB_CFGR2_PWM0CKS

#define RCC_BUZCLK_ILRC           			((uint32_t)0x00000000)
#define RCC_BUZCLK_IHRC_DIV750				APB_CFGR2_BUZ0CKS		

#define RCC_RTCCLK_XTOSC1            		((uint32_t)0x00000000)
#define RCC_RTCCLK_ILRC           			APB_CFGR2_RTCCKS_0
#define RCC_RTCCLK_IHRC						APB_CFGR2_RTCCKS_1	

#define RCC_UARTCLK_IHRC					((uint32_t)0x00000000)	
#define RCC_UARTCLK_XTOSC2          		APB_CFGR2_U0CKS_0
#define RCC_UARTCLK_SYSCLK         		    APB_CFGR2_U0CKS_1

#define RCC_I2CCLK_SYSCLK         		    ((uint32_t)0x00000000)
	
#define IS_RCC_APB2_PERCLK(PERCLK)  (((PERCLK)==RCC_PWMCLK_IHRC)||((PERCLK)==RCC_PWMCLK_ILRC)||\
                                     ((PERCLK)==RCC_PWMCLK_XTOSC1) ||((PERCLK)==RCC_PWMCLK_XTOSC2)||\
									 ((PERCLK)==RCC_BUZCLK_IHRC_DIV750) ||((PERCLK)==RCC_BUZCLK_ILRC) ||\
									 ((PERCLK)==RCC_RTCCLK_IHRC) ||((PERCLK)==RCC_RTCCLK_ILRC) ||\
									 ((PERCLK)==RCC_RTCCLK_XTOSC1)||\
									 ((PERCLK)==RCC_UARTCLK_IHRC)||((PERCLK)==RCC_UARTCLK_SYSCLK)||\
									 ((PERCLK)==RCC_UARTCLK_XTOSC2))

					

/* @defgroup Configure the PeriPheral of APB2  clock prescaler */

#define RCC_PWMCLK_DIV1					    ((uint32_t)0x00000000)	
#define RCC_PWMCLK_DIV2           			APB_CFGR2_PWM0CD_0
#define RCC_PWMCLK_DIV4            		    APB_CFGR2_PWM0CD_1
#define RCC_PWMCLK_DIV8         			APB_CFGR2_PWM0CD

#define RCC_I2CCLK_DIV2						((uint32_t)0x00000000)	
#define RCC_I2CCLK_DIV4           			APB_CFGR2_I2CCD_0
#define RCC_I2CCLK_DIV8            		    APB_CFGR2_I2CCD_1
#define RCC_I2CCLK_DIV16            		APB_CFGR2_I2CCD

#define IS_RCC_APB2_PERDIV(PERDIV)	(((PERDIV)==RCC_PWMCLK_DIV1) ||((PERDIV)==RCC_PWMCLK_DIV2)||\
                                     ((PERDIV)==RCC_PWMCLK_DIV4) ||((PERDIV)==RCC_PWMCLK_DIV8)||\
									 ((PERDIV)==RCC_I2CCLK_DIV2) ||((PERDIV)==RCC_I2CCLK_DIV4)||\
									 ((PERDIV)==RCC_I2CCLK_DIV8) ||((PERDIV)==RCC_I2CCLK_DIV16)) 

/** @defgroup RCC_FLAG 复位标志位
  * @
  */
#define RCC_FLAG_IHRCRDY					IHRC_CR_IHRCOK  //高频时钟准备就绪
#define RCC_FLAG_HSWIF						MCLK_CFGR_HSWIF  //发生硬件自动切换系统时钟
  
#define RCC_FLAG_PORRST						RST_SR_POR_RSTF		
#define RCC_FLAG_WWDGRST            		RST_SR_WWDG_RSTF
#define RCC_FLAG_IWDGRST             		RST_SR_IWDG_RSTF
#define RCC_FLAG_SFTRST            			RST_SR_SFT_RSTF
#define RCC_FLAG_PINRST              		RST_SR_PIN_RSTF
#define RCC_FLAG_OBLRST              		RST_SR_OBL_RSTF
#define RCC_FLAG_BORRST              		RST_SR_BOR_RSTF
#define RCC_FLAG_RSTERR              		RST_SR_RST_ERR

#define IS_RCC_FLAG(FLAG) (((FLAG)==RCC_FLAG_IHRCRDY)||((FLAG)==RCC_FLAG_HSWIF)||\
                           ((FLAG)==RCC_FLAG_PORRST)||((FLAG)==RCC_FLAG_WWDGRST)||\
						   ((FLAG)==RCC_FLAG_IWDGRST)||((FLAG)==RCC_FLAG_SFTRST)||\
						   ((FLAG)==RCC_FLAG_PINRST)||((FLAG)==RCC_FLAG_BORRST)||\
						   ((FLAG)==RCC_FLAG_OBLRST)||((FLAG)==RCC_FLAG_RSTERR)) 
						   						   

/** @defgroup RCC_Clockout */
#define RCC_CLKOUT_SYSCLK					((uint8_t)0x00)	
#define RCC_CLKOUT_IHRC           			CLKOUT_CR_CLKOUTS_0
#define RCC_CLKOUT_ILRC             		CLKOUT_CR_CLKOUTS_1
#define RCC_CLKOUT_XTOSC1          			((uint8_t)0x03)
#define RCC_CLKOUT_XTOSC2_DIV2				CLKOUT_CR_CLKOUTS_2	
#define RCC_CLKOUT_TMR0CLK           		((uint8_t)0x05)
#define RCC_CLKOUT_TMR1CLK             		((uint8_t)0x06)
#define RCC_CLKOUT_TMR2CLK          		CLKOUT_CR_CLKOUTS
             
#define IS_RCC_CLKOUT(RCC_CLKOUT) (((RCC_CLKOUT)==RCC_CLKOUT_SYSCLK)||((RCC_CLKOUT)==RCC_CLKOUT_IHRC)||\
                           ((RCC_CLKOUT)==RCC_CLKOUT_ILRC)||((RCC_CLKOUT)==RCC_CLKOUT_XTOSC1)||\
						   ((RCC_CLKOUT)==RCC_CLKOUT_XTOSC2_DIV2)||((RCC_CLKOUT)==RCC_CLKOUT_TMR0CLK)||\
						   ((RCC_CLKOUT)==RCC_CLKOUT_TMR1CLK)||((RCC_CLKOUT)==RCC_CLKOUT_TMR2CLK)) 
	
#define IS_XTOSC1_Idrive(Idrive) (((Idrive) >= 0)&&((Idrive) <= 0x0F))
#define IS_XTOSC2_Idrive(Idrive) (((Idrive) >= 0)&&((Idrive) <= 0x0F))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

/************************RCC 时钟相关设置****************************/
void RCC_DeInit(void);                                                                      //将RCC相关寄存器恢复成上电默认值

void RCC_CLKSourceCmd(uint32_t RCC_CLKSource,FunctionalState NewState);						//时钟源的使能和关闭
void RCC_ClockOut(uint8_t RCC_CLKOUT,FunctionalState NewState);			                    //时钟源的输出

void RCC_IHRCCHOPPERCmd(FunctionalState NewState);						                    //IHRC内部CHOPPER使能,该位无特别需求时，请保持默认值
void RCC_LoadIHRCALValue(void);                                                             //自动载入IHRC校准值 
void RCC_AdjustIHRCALValue(uint8_t IHRCALValue);                                            //手动调整IHRC校准值 

void RCC_LoadILRCALValue(void);                                                             //自动载入ILRC校准值 
void RCC_AdjustILRCALValue(uint8_t ILRCALValue);                                            //手动调整ILRC校准值

void RCC_SetSYSCLKDefault(void);			                                                //系统时钟为过渡时钟IHRC/2
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLK,uint32_t SYSCLKDIV);	                            //实现系统时钟的切换

/* Peripheral clocks configuration functions **********************************/
void RCC_APB1PeriphClockConfig(uint32_t RCC_APBPeriph,uint8_t RCC_TMCLK,uint8_t RCC_TMCLK_DIV);	                //主要实现APB1外设TM0/TM1/TM2的时钟配置								
void RCC_APB2PeriphClockConfig(uint32_t RCC_APBPeriph,uint32_t Periph2CLKSource,uint32_t Periph2CLKDIV);		//主要实现APB外设PWM0/1/BUZ0/1/RTC/I2C/UART0/1的时钟配置

void RCC_APBPeriphClockCmd(uint32_t RCC_APBPeriph, FunctionalState NewState);                                   //外设时钟使能

void RCC_APBPeriphResetCmd(uint32_t RCC_APBPeriph, FunctionalState NewState);                                   //恢复APB相关外设寄存器值为上电默认值
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);                                   //使能FLASH接口电路和SRAM时钟
void RCC_XTOSC_RESCmd(FunctionalState NewState);                                                                //晶振内部RF电阻使能(默认使能)

/* Interrupts and flags management functions **********************************/

RSTStatus RCC_GetResetFlagStatus(uint32_t RCC_FLAG);          //获取复位状态标志，IHRC准备完成标志，发生硬件自动切换标志
void RCC_ClearResetFlagStatus(void);                          //清除芯片复位标志，不包含清发生硬件自动切换系统时钟标志
void RCC_ClearHSWFlagStatus(void);                            //清除发生硬件自动切换系统时钟标志

void RCC_XTOSC1CheckCmd(FunctionalState NewState);	          //使能XTOSC1停振检测功能
void RCC_XTOSC2CheckCmd(FunctionalState NewState);            //使能XTOSC2停振检测功能

FlagStatus RCC_GetXTOSC1CheckStatus(void);                    //获取XTOSC1停振检测状态标志位
FlagStatus RCC_GetXTOSC2CheckStatus(void);                    //获取XTOSC2停振检测状态标志位

void RCC_XTOSC1ITCmd(FunctionalState NewState); 	          //XTOSC1停振检测中断使能
void RCC_XTOSC2ITCmd(FunctionalState NewState);	              //XTOSC2停振检测中断使能

ITStatus RCC_GetXTOSC1ITStatus(void);                         //获取XTOSC1停振检测中断标志位
ITStatus RCC_GetXTOSC2ITStatus(void);                         //获取XTOSC2停振检测中断标志位

void RCC_ClearXTOSC1ITStatus(void);                           //清除XTOSC1停振检测中断标志位
void RCC_ClearXTOSC2ITStatus(void);                           //清除XTOSC2停振检测中断标志位

void XTOSC1_SetDriveCurrent(uint8_t Idrive);                  //XTOSC1驱动电流设置
void XTOSC2_SetDriveCurrent(uint8_t Idrive);                  //XTOSC2驱动电流设置
/*******************************************************/

//uint32_t RCC_GetRCCREGValue(uint32_t RCC_TypeDef*REG);  //获取RCC相关寄存器的值										

#ifdef __cplusplus
}
#endif

#endif /* __SD93F115B_RCC_H */

/*****************************END OF FILE********************************/